This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-088963, filed Mar. 28, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor memory device, for example, a dynamic random access memory (DRAM), and in particular, to a semiconductor memory device having a function of switching data lines based on a data line-shifting redundancy method to relieve defective columns and testing redundancy cells.
A semiconductor memory device such as a DRAM is provided with redundancy memory cells in addition to normal memory cells and comprises a redundant circuit to relieve some defective cells randomly present in the normal memory cells. The defective cells are replaced with redundant rows or columns using as relieved units defective rows or columns in which the defective cells are present.
In a normal redundant circuit, a fuse circuit storing defective address data is mounted on a memory chip. Address data input to the memory are compared with data stored in the fuse circuit, and when the data are equal, a replacement signal is generated to select redundant rows or columns for defective rows or columns.
Then, the defective column relieve method is focused on. When the defective columns are correlated with the redundant columns on a one-to-one correspondence, the scale of the column redundant circuit must be increased if an attempt is made to increase defective column relieve efficiency.
Thus, as a method for making it possible to efficiently relieve defective columns with a smaller-scale circuit, a data line-shifting redundant circuit based on shifting of data lines is disclosed, for example, in Jpn. Pat. Appln. KOKAI Publication No. 3-176899 and No. 5-101648.
In the data line-shifting redundant circuit disclosed in these publications, when a defective address corresponding to a defective column is input, a data line that outputs readout data corresponding to this defective column is replaced with an adjacent normal data line for use. For the addresses following this defective address, data lines are subjected to shift control so as to be sequentially shifted in such a manner that only normal data lines including a spare data line arranged at an end of the array of the data lines are connected to a data I/O line.
A conventional column redundant circuit provided in a DRAM will be described below.
FIG. 1 is a block diagram showing an example of the configuration of a conventional column redundant circuit.
A switching circuit 11 switches a connection to a memory cell array 12 between a first group of data lines I/O LINES #1 and a second group of data lines I/O LINES #2 in order to transfer readout/write data to and from the memory cell array 12. The switching circuit 11 has its operation controlled by means of a switch status signal issued by an analyzer 13 according to a column address signal CA.
FIG. 2 is a block diagram showing an example of a configuration where a data line-shifting redundant circuit is provided as the column redundant circuit in FIG. 1.
The switching circuit 11 is controlled by means of the switch status signal so as to switch a connection path between the first group of data lines I/O LINES #1 and the second group of data lines I/O LINES #2 based on the data line shifting method.
Repeated structures (the portions enclosed by dot lines) in the switching circuit 11 are each called an I/O unit 11A.
Each I/O unit 11A has an I/O number that is information on itself. The I/O number is often an address.
The switch status signal output from the analyzer 13 according to each column address signal CA is represented by a shift number corresponding to the I/O number. Thus, a fuse circuit is provided which is composed of a plurality of fuse elements storing information (reconnection information) on the correlationship between the column address signals CA and the switch status signals. FIG. 2 shows an operational state in which a shift number 4 is issued as the switch status signal.
The I/O units 11A having an I/O number equal to or larger than the shift number issued by the analyzer 13 performs a shift operation such that each relevant data line of the group of data lines I/O LINES #2 is connected to one of the group of data lines I/O LINES #1 which is adjacent to another of the data lines I/O LINES 1 which corresponds to the first data line. In FIG. 2, all the I/O units 11A having an I/O number of 4 or more execute reconnections.
In the data line-shifting redundant circuit in FIG. 2, a start point for data line shifting which corresponds to a defective column address is stored in a fuse element in the fuse circuit 14. In this configuration, however, with a large number of data lines of the first and second groups, a large number of selection signal lines (shift number transfer lines) for shift-controlling the data lines are required, thus complicating the configuration of the switching circuit 11 for shifting the data lines.
Thus, an improved data line-shifting redundant circuit that requires a reduced number of selection signal lines for shift-controlling the data lines has been proposed. This data line-shifting redundant circuit has a configuration such as that shown in FIG. 3.
This circuit differs from the data line-shifting redundant circuit shown in FIG. 2 in that the I/O numbers provided for the I/O units 11A are not the addresses but numbers varying with groups.
In this case, the plurality of I/O units 11A can be classified into groups each of which has the same redundancy status despite the variation of the column address CA.
The circuit additionally has an I/O numbering circuit 15 for providing numbers varying with the group, as the I/O numbers provided to the I/O units 11A. For example, the plurality of I/O units 11A are represented as lower units having lower I/O numbers (in the left of the figure) and higher units on the opposite side (in the right of the figure).
In addition to the fuse circuit 14 having the information (reconnection information) on the correlationship between the column address signals CA and the switch status signals, a fuse circuit 16 is provided which has a plurality of fuse elements storing information (reconnection information) on the correlationship between the I/O units 11A and the I/O numbers.
FIG. 3 shows an operational state in which a shift number 1 is issued as the shift status signal. This configuration makes it possible to reduce the varying range of the value of the shift number, thus reducing the number of wires for transmitting the shift status to the I/O units 11A.
In a DRAM having the data line-shifting redundant circuit, it is assumed that the circuit is provided with a forced access mode for forcibly accessing memory cells regardless of the storage statuses of the fuse circuits storing the reconnection information. A mode in which memory cells are accessed while reconnections are being carried out in order to relieve defective memory cells is called an xe2x80x9cnormal access modexe2x80x9d.
If the forced access mode is added to the circuit, it can be implemented using a certain method. A specific example of a circuit with the forced access mode added thereto is the configuration shown in FIGS. 4 and 5.
The circuit in FIG. 4 is a DRAM having the data line-shifting redundant circuit in FIG. 3, the DRAM being configured so that in a test mode, the switch status signal determined by the column address CA is neglected, while the switch status signal with the shift number 4 is output to the I/O units 11A. In this case, no I/O unit 11A has a shift number equal to or larger than 4, reconnections are not carried out, that is, reconnections are forcibly disabled (forcibly disabling status), thus making irrelevant the storage statuses of the fuse circuits having the reconnection information.
On the other hand, the circuit in FIG. 5 is a DRAM having the data line-shifting redundant circuit, the DRAM being configured so that in the test mode, the switch status signal determined by the column address CA is neglected, while the shift status signal having a shift number xe2x88x921 is output to the I/O units 11A. In this case, for all the switch status signals and all the I/O numbers, xe2x80x9cI/O numberxe2x80x9dxe2x89xa7xe2x80x9cswitch numberxe2x80x9d is established, that is, reconnections are forcibly executed (forcibly enabling status), thus making irrelevant the storage statuses of the fuse circuits having the reconnection information.
Next, considerations required to implement the forced access mode using the method for changing the switch status signal as described above will be described.
In the test mode, if the shift status signal with the shift number 4 or xe2x88x921 is output to the I/O units 11A, a logic circuit for determining whether the circuit is in the normal or forced access mode must be incorporated in the circuit for generating the switch status signal.
The switch status signal, however, is determined by the column address CA, which varies at a very high speed, so that the logic circuit incorporated in the circuit for generating the switch status signal as described above may reduce the speed at which memory cells are accessed in the normal access mode. Further, it is undesirable in terms of the characteristics of the test mode that the switch status signal, varying at a very high speed, passes along different signal paths in the normal access mode and in the forced access mode.
The present invention is adapted to solve the above problems, and it is an object thereof to provide a semiconductor memory device which can reduce the varying range of the value of a shift number to thereby reduce the number of wires for transmitting a switch status signal to I/O units and which can restrain a decrease in a memory access speed in the normal access mode even if memory cells are forcibly accessed irrespective of the contents of a memory circuit having reconnection information.
According to a first aspect of the present invention, there is provided a semiconductor memory device comprising a memory cell array including memory cells arranged in a matrix and having a plurality of columns, at least one redundant column cell array provided adjacent to the memory cell array, for relieving defective columns in the memory cell array, a plurality of data lines for transferring readout data read out from the memory cell array or write data to be written to the memory cell array, at least one spare data line provided adjacent to the plurality of data lines, for transferring readout data read out from the redundant column cell array or write data to be written to the redundant column cell array, a plurality of I/O lines provided correspondingly to the plurality of data lines, for transmitting and receiving readout/write data to and from the plurality of data lines, a data line-shifting circuit for receiving a shift control signal and controlling connections between the plurality of I/O lines and both the plurality of data lines and the at least one spare data line based on the shift control signal, a first I/O number generating circuit for generating, as locational information assigned to each of the plurality of I/O lines, shift indicating numbers that increment by one for each of a plurality of I/O lines starting with the I/O line corresponding to the data line to transfer data on a defective one of the plurality of columns, the plurality of I/O lines including the above-mentioned I/O line and arranged on one side relative to the above-mentioned I/O line, a second I/O number generating circuit for generating shift indicating numbers all having the same value, as locational information assigned to each of the plurality of I/O lines, a shift indicating number selecting circuit for selecting shift indicating numbers generated by the first and second I/O number generating circuits, a shift indicating number memory circuit for storing the shift indicating numbers selected by the shift indicating number selecting circuit, a selection circuit for storing the correlationship between the addresses of the defective columns and the shift indicating numbers and outputting a selection signal corresponding to the shift indicating numbers when the address of the defective column is input, and a shift control circuit to which the selection signal output from the selection circuit and the shift indicating signal stored in the shift indicating number memory circuit are input and which compares the selection signal and the shift indicating number together to output the shift control signal to the data line-shifting circuit based on a result of the comparison, wherein if the shift indicating number selecting circuit selects the shift indicating number generated by the first I/O number generating circuit, the data line shifting circuit receives the shift control signal output from the shift control circuit and performs a first connection control operation of excluding the data line to transfer data on the defective column to sequentially shift a plurality of data lines adjacent to the excluded data line on one side thereof before correspondingly connecting the shifted data lines and the at least one spare data line to the plurality of I/O lines.
According to a second aspect of the present invention, there is provided a semiconductor memory device comprising a memory cell array including memory cells arranged in a matrix and having a plurality of columns, at least one redundant column cell array provided adjacent to the memory cell array, for relieving defective columns in the memory cell array, a plurality of data lines for transferring readout data read out from the memory cell array or write data to be written to the memory cell array, at least one spare data line provided adjacent to the plurality of data lines for transferring readout data read out from the redundant column cell array or write data to be written to the redundant column cell array, a plurality of I/O lines provided correspondingly to the plurality of data lines so as to transmit and receive readout/write data to and from the plurality of data lines, a data line shifting circuit for receiving a shift control signal and controlling connections between the plurality of I/O lines and both the plurality of data lines and the at least one spare data line based on the shift control signal, a I/O number generating circuit for generating, as locational information assigned to each of the plurality of I/O lines, shift indicating numbers that increment by one for each of a plurality of I/O lines starting with the I/O line corresponding to the data line to transfer data on a defective one of the plurality of columns, the plurality of I/O lines including the above-mentioned I/O line and arranged on one side relative to the above-mentioned I/O line, a shift indicating number modifying circuit for modifying all the shift indicating numbers generated by the I/O number generating circuit so as to have the same value, a selection circuit for storing the correlationship between the addresses of the defective columns and the shift indicating numbers and outputting a selection signal corresponding to the shift indicating number when the address of the defective column is input, and a shift control circuit to which the selection signal output from the selection circuit and the shift indicating signal stored in the shift indicating number memory circuit are input and which compares the selection signal and the shift indicating number together to output the shift control signal to the data line shifting circuit based on a result of the comparison, wherein if the shift indicating number modifying circuit does not modify the shift indicating number, the data line shifting circuit receives the shift control signal output from the shift control circuit and performs a first connection control operation of excluding the data line to transfer data on the defective column to sequentially shift a plurality of data lines adjacent to the excluded data line on one side thereof before correspondingly connecting the shifted data lines and the at least one spare data line to the plurality of I/O lines.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.